The invention relates to a method to enhance grain size in polycrystalline silicon, called polysilicon. Larger grain size in polysilicon is advantageous for many uses, particularly in thin film transistors (TFTs).
One of the major obstacles to the use of polysilicon thin film as a semiconductor in active devices is the relatively small grain sizes (around 0.05 micron or less) of polysilicon thin films deposited by such methods as low-pressure chemical vapor deposition and sputtering. A film with small grain size has a larger number of grain boundaries, decreasing carrier mobility. Typical electron mobilities in polysilicon films made using these methods are on the order of 10 cm2/volt-second, two orders of magnitude lower than electron mobilities in bulk silicon.
The poor electrical performance caused by grain boundaries in the channel region limits the use of TFTs largely to low-temperature flat panel displays. It is believed that electrical properties of TFTs can be improved if the grain size is enhanced and the number of grain boundaries in the channel region minimized.
There is a need, therefore, to enhance grain size in polysilicon thin films.
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains.
A preferred embodiment provides for a method for crystallizing silicon, the method comprising embedding deposited silicon nuclei within a matrix of amorphous silicon and crystallizing from the embedded silicon nuclei.
Another preferred embodiment provides for a method for crystallizing silicon. The method comprises depositing a first layer of amorphous silicon; depositing silicon nuclei on the first layer of amorphous silicon; depositing a second layer of amorphous silicon over the first layer and the nuclei, wherein conversion of the first layer to hemispherical grains before deposition of the second layer is substantially prevented; and annealing the first and second layers of amorphous silicon to induce crystallization. A related embodiment provides for a thin film transistor comprising polysilicon, wherein the polysilicon is formed by such a method.
In a different preferred-embodiment, a monolithic three dimensional memory array comprising memory cells, said memory cells comprising polysilicon, is provided for. In this embodiment, any of said polysilicon is crystallized by a method comprising embedding deposited silicon nuclei between layers of amorphous silicon and crystallizing from the embedded silicon nuclei. A related embodiment provides for a thin film transistor comprising a channel region formed by a method comprising embedding deposited silicon nuclei between layers of amorphous silicon; and annealing the nuclei and amorphous silicon layers.
Another embodiment provides for a method for crystallizing silicon, the method comprising depositing a first layer of amorphous silicon, depositing silicon nuclei on the first layer of amorphous silicon, changing conditions to inhibit formation of hemispherical grains, depositing a second layer of amorphous silicon over the first layer and nuclei, and annealing the nuclei and silicon layers.
Other preferred embodiments arc provided, and each of the preferred embodiments can be used alone or in combination with one another.